Simulation of pixel-size impact for optical brightfield wafer defect inspection

Introduction

These days, we do not get by a day without technology. Yet, we hardly stop to think about the very foundations that allow our way of life: semiconductors. Notably so, as the early computers took up a huge room. Today, we hold them in our palms, and fork out hundreds or thousands of dollars to buy them. With the world revolving around digital transformation and technology, the pressure is on semiconductor manufacturers to take on ever increasing challenges of creating higher complexity chip designs, explore new processes and materials. They also have to grapple with yield loss, which is an ever-present problem.

Typically, advanced semiconductor nodes are made by combining many processes together on a silicon wafer to fabricate the dies containing the intended designs. The dies are then diced into individual chips before being packaged and shipped. As complexity grows, so does the number of processes, and thus the manufacturing steps. These are all inception points for defects, which can cause the chips to fail and discarded. The earlier the defects can be caught, the less material wastage. Since fabs achieve economies of scale by high volume manufacturing, every discarded chip eats into operating margin. If the yield of a fab is low, these costs get passed onto the device manufacturer, and ultimately onto us, the consumers! Therefore, it is clear that yield control and improvement is critical and can be achieved by inspecting the dies before they proceed with wafer packaging.

Appendix

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